This invention relates generally to decimal floating point addition, and more particularly, to decimal floating point addition using multiple concurrent paths.
Decimal floating point has been used in calculators for many years but for the first time is becoming part of an IEEE standard (754R Floating Point Standard). Addition is the primary arithmetic instruction and it is critical to the performance of a decimal floating point unit. Floating point arithmetic is more complex than fixed point arithmetic due to the requirement to align the operations. Typically, the time required for a decimal floating point addition or subtraction operation is limited to the time required for the case where both operands must be shifted prior to the adder operation. Decimal floating point formats, as defined by the IEEE 754R standard, include a double word format containing sixteen digits for the coefficient and a quad word format containing thirty-four digits for the coefficient. Note that the coefficients are integer and are not normalized and therefore, can contain leading zeros. With the advent of the new standard and the increase in the use of decimal arithmetic operations for financial calculations, it becomes desirable to implement these operations at a high performance.